XP2 Datasheet, PDF (14/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Architecture
LatticeXP2 Family Data Sheet
Edge Clock Sources
Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be
driven from adjacent edge clock PIOs, primary clock PIOs, PLLs and clock dividers as shown in Figure 2-8.
Figure 2-8. Edge Clock Sources
Clock Input
From
Routing
Clock Input
From
Routing
Sources for top
edge clocks
PLL
Input
CLKOP
GPLL _CLKOS
CLKOP
CLKOS GPLL
PLL
Input
From Routing
Clock
Input
Clock
Input
From Routing
PLL
Input
CLKOP
GPLL _CLKOS
Eight Edge Clocks (ECLK)
Two Clocks per Edge
CLKOP
CLKOS GPLL
From Routing
Clock
Input
Clock
Input
From Routing
PLL
Input
Sources for left edge clocks
From
Routing
Clock Input
Sources for
bottom edge
clocks
From
Routing
Clock Input
Sources for right edge clocks
Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs.
2-11