XP2 Datasheet, PDF (20/92 Pages) Lattice Semiconductor – LatticeXP2 Family Data Sheet

Lattice Semiconductor
Figure 2-16. FlashBAK Technology
Make Infinite Reads and
Writes to EBR
Architecture
LatticeXP2 Family Data Sheet
Flash
Write to Flash During
Programming
JTAG / SPI Port
FPGA Logic
EBR
Write From Flash to
EBR During Configuration /
Write From EBR to Flash
on User Command
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
EBR memory supports two forms of write behavior for single port or dual port operation:
1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode
is supported for all data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively. GSRN, the global reset signal, resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2-17.
Figure 2-17. Memory Core Reset
RSTA
Memory Core
Q D ^SET
LCLR
Output Data
Latches
Q D ^SET
LCLR
Port A[17:0]
Port B[17:0]
RSTB
GSRN
Programmable Disable
2-17