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HYB25D512800BT Datasheet, PDF (9/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM | |||
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512Mbit Double Data Rate SDRAM
DDR SDRAM
HYB25D512[40/80/16]0B[C/T]
HYB25D512[40/80/16]0B[E/F]
1
Overview
1.1
Features
⢠Double data rate architecture: two data transfers per clock cycle
⢠Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the
receiver
⢠DQS is edge-aligned with data for reads and is center-aligned with data for writes
⢠Differential clock inputs (CK and CK)
⢠Four internal banks for concurrent operation
⢠Data mask (DM) for write data
⢠DLL aligns DQ and DQS transitions with CK transitions
⢠Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
⢠Burst Lengths: 2, 4, or 8
⢠CAS Latency: (1.5), 2, 2.5, 3
⢠Auto Pre charge option for each burst access
⢠Auto Refresh and Self Refresh Modes
⢠7.8 µs Maximum Average Periodic Refresh Interval
⢠2.5 V (SSTL_2 compatible) I/O
⢠VDDQ = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
⢠VDD = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
⢠P-TFBGA-60 and P-TSOPII-66 package
Table 1 Performance
Product Type Speed Code
Speed Grade
max. Clock Frequency
@CL3
@CL2.5
@CL2
fCK3
fCK2.5
fCK2
-5
DDR400B
200
166
133
-6
DDR333B
166
166
133
-7
DDR266A
143
143
133
Unit
â
MHz
MHz
MHz
Data Sheet
9
Rev. 1.2, 2004-06
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