HYB25D512800BT Datasheet, PDF (38/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
CK
CK
Command
Address
DQS
DQ
DM
CAS Latency = 2
Read
BAa, COL n
BST
CL=2
NOP
Write
BAa, COL b
NOP
NOP
t_DQSS (min)
DOa-n
DI a-b
CAS Latency = 2.5
Read
BAa, COL n
BST
NOP
NOP
CL=2.5
DOa-n
Write
BAa, COL b
NOP
t_DQSS (min)
Dla-b
DO a-n = data out from bank a, column n
.DI _{a-b = data in to bank a, column b}
1 subsequent elements of data out appear in the programmed order following DO a-n.
Data In elements are applied following Dl a-b in the programmed order, according to burst length.
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Figure 15 Read to Write: CAS Latencies (Burst Length = 4 or 8)
Don’t Care
Data Sheet
38
Rev. 1.2, 2004-06