HYB25D512800BT Datasheet, PDF (20/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

Figure 4 Block Diagram 512Mbit 64 Mbit ×8
Data Sheet
20
Row-Address MUX Refresh Counter
Address Register
Bank Control Logic
Bank0
Row-Address Latch
& Decoder
Drivers
Read Latch
Receivers
HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Pin Configuration
Rev. 1.2, 2004-06