HYB25D512800BT Datasheet, PDF (48/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
Minimum DQSS, Odd Number of Data (3-bit Write),Interrupting (CAS Latency = 2; Burst Length = 8)
CK
CK
Command
Address
DQS
DQ
DM
T1
T2
T3
T4
T5
T6
Write
BAa, COL b
NOP
NOP
t_DQSS (min)
NOP
Read
NOP
t_WTR
BAa, COL n
CL = 2
DI a-b
1
2
2
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
t_WTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
Figure 24 Write to Read: Minimum DQSS, Odd Number of Data, Interupting
Data Sheet
48
Rev. 1.2, 2004-06