HYB25D512800BT Datasheet, PDF (46/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
Maximum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
NOP
BAa, COL b
t_DQSS (max)
DI a-b
NOP
Read
NOP
t_WTR
BAa, COL n
CL = 2
CK
CK
Command
Address
DQS
DQ
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
NOP
BAa, COL b
t_DQSS (min)
DI a-b
NOP
Read
NOP
t_WTR
BAa, COL n
CL = 2
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
t_WTR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands may be to any bank.
Don’t Care
Figure 22 Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Data Sheet
46
Rev. 1.2, 2004-06