HYB25D512800BT Datasheet, PDF (72/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Normal Strength Pull-down and Pull-up Characteristics
5.2.1
I_DD Current Measurement Conditions
I_DD1: Operating Current: One Bank Operation
1. Only one bank is accessed with t_RCMIN. Burst Mode, Address and Control inputs on NOP edge are changing
once per clock cycle. I_OUT = 0 mA.
2. Timing patterns
a) DDR266A (133 MHz, CL = 2): t_CK = 7.5 ns, CL = 2, BL = 4, t_RCD = 3 × t_CK, t_RC = 9 × t_CK, t_RAS = 5 × t_CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N NN - repeat the same timing with random address changing
50% of data changing at every burst
b) DDR333 (166 MHz, CL = 2.5): t_CK = 6 ns, CL = 2.5, BL = 4, t_RCD = 3 × t_CK, t_RC = 9 × t_CK, t_RAS = 5 × t_CK
Setup: A0 N N R0 N P0 N N N
Read: A0 N N R0 N P0 N N N - repeat the same timing with random address changing
50% of data changing at every burst
c) DDR400 (200 MHz, CL = 3): t_CK = 5 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 11 × t_CK, t_RAS = 8 × t_CK
Setup: A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
50% of data changing at every burst
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
I_DD7: Operating Current: Four Bank Operation
1. Four banks are being interleaved with t_RCMIN. Burst Mode, Address and Control inputs on NOP edge are not
changing. I_OUT = 0 mA.
2. Timing patterns
a) DDR266A (133 MHz, CL = 2): t_CK = 7.5 ns, CL = 2, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 × t_CK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
b) DDR333 (166 MHz, CL = 2.5): t_CK = 6 ns, CL = 2.5, BL = 4, t_RRD = 2 × t_CK, t_RCD = 3 × t_CK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
c) DDR400 (200 MHz, CL = 3): t_CK = 5 ns, BL = 4, t_RCD = 3 × t_CK, t_RC = 11 × t_CK, t_RAS = 8 × t_CK
Setup: A0 N N R0 N N N N P0 N N
Read: A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
50% of data changing at every burst
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
Data Sheet
72
Rev. 1.2, 2004-06