HYB25D512800BT Datasheet, PDF (30/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
3.5
Operations
3.5.1 Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must
be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see
Figure 7), which decode and select both the bank and the row to be activated. After opening a row (issuing an
Active command), a Read or Write command may be issued to that row, subject to the t_RCD specification. A
subsequent Active command to a different row in the same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval between successive Active commands to the same
bank is defined by t_RC. A subsequent Active command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access overhead. The minimum time interval between
successive Active commands to different banks is defined by t_RRD.
CK
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
HIGH
RA
BA
RA = row address.
BA = bank address.
Don’t Care
Figure 7 Activating a Specific Row in a Specific Bank
CK
CK
Command
A0-A12
BA0, BA1
ACT
ROW
BA x
NOP
t_RRD
Figure 8 t_RCD and t_RRD Definition
ACT
ROW
BA y
NOP
NOP
t_RCD
RD/WR
COL
BA y
NOP
NOP
Don’t Care
Data Sheet
30
Rev. 1.2, 2004-06