HYB25D512800BT Datasheet, PDF (44/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
T1
T2
T3
Write
NOP
BAa, COL b
t_DQSS (max)
DI a-b
NOP
T4
Write
BAa, COL n
DI a-b, etc. = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
T5
NOP
DI a-n
Don’t Care
Figure 20 Write to Write: Max. DQSS, Non-Consecutive (Burst Length = 4)
Data Sheet
44
Rev. 1.2, 2004-06