HYB25D512800BT Datasheet, PDF (29/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
Table 8 Truth Table 1a: Commands
Name (Function)
CS RAS CAS WE Address MNE Notes
Deselect (NOP)
H X X XX
NOP
1)2)
No Operation (NOP)
L H H HX
NOP
1)2)
Active (Select Bank And Activate Row)
LL
H
H Bank/Row ACT ¹⁾³⁾
Read (Select Bank And Column, And Start Read Burst) L H L H Bank/Col Read ¹⁾⁴⁾
Write (Select Bank And Column, And Start Write Burst) L H L L Bank/Col Write ¹⁾⁴⁾
Burst Terminate
L H H LX
BST
1)5)
Precharge (Deactivate Row In Bank Or Banks)
L L H L Code
PRE
1)6)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X
AR/SR ¹⁾⁷⁾⁸⁾
Mode Register Set
LL
L
L Op-Code MRS ¹⁾⁹⁾
1) CKE is HIGH for all commands shown except Self Refresh.
V_REF must be maintained during Self Refresh operation
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A12 provide row address.
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for ×16, i = 9 for ×8 and 9, 11 for ×4);
A10 HIGH enables the Auto Precharge feature (non persistent), A10 LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read
bursts with Auto Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to
be written to the selected Mode Register).
Table 9 Truth Table 1b: DM Operation
Name (Function)
Write Enable
Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
DM DQs Notes
L
Valid ¹⁾
H
X
1)
Data Sheet
29
Rev. 1.2, 2004-06