HYB25D512800BT Datasheet, PDF (67/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Normal Strength Pull-down and Pull-up Characteristics
5.2
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, I_DD Specifications and Conditions, and Electrical Characteristics and AC Timing.)
Note:
1. All voltages referenced to V_SS.
2. Tests for AC timing, I_DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/
supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage
range specified.
3. Figure 38 represents the timing reference load used in defining the relevant timing parameters of the part. It
is not intended to be either a precise representation of the typical system environment nor a depiction of the
actual load presented by a production tester. System designers will use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers will correlate to their production
test conditions (generally a coaxial transmission line terminated at the tester electronics).
4. AC timing and I_DD tests may use a V_IL to V_IH swing of up to 1.5 V in the test environment, but input timing is
still referenced to V_REF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for
the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/
ns in the range between V_IL(AC) and V_IH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal
does not ring back above (below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR
SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the
latest JEDEC specification for DDR components.
Output
(V_OUT)
V_TT
50 Ω
Timing Reference Point
30 pF
Figure 38 AC Output Load Circuit Diagram / Timing Reference Load
AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100
Parameter
Symbol –5
–6
–7
DDR400B DDR333
DDR266A
Min. Max. Min. Max. Min. Max.
DQ output access time from CK/ t_AC
CK
–0.5 +0.5 –0.7 +0.7 –0.75 +0.75
DQS output access time from CK/ t_DQSCK –0.5 +0.5 –0.6 +0.6 –0.75 +0.75
CK
CK high-level width
CK low-level width
t_CH
0.45 0.55 0.45 0.55 0.45 0.55
t_CL
0.45 0.55 0.45 0.55 0.45 0.55
Unit Note/ Test
Condition
1)
ns
2)3)4)5)
ns
2)3)4)5)
t_CK
2)3)4)5)
t_CK
2)3)4)5)
Data Sheet
67
Rev. 1.2, 2004-06