HYB25D512800BT Datasheet, PDF (21/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

Rev. 1.2, 2004-06
21
Data Sheet
Figure 5 Block Diagram 512Mbit 32 Mbit ×16
Row-Address MUX Refresh Counter
Address Register
Bank Control Logic
Bank0
Row-Address Latch
& Decoder
Drivers
Read Latch
Receivers
HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Pin Configuration