HYB25D512800BT Datasheet, PDF (50/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
DM
CK
CK
Command
Address
DQS
DQ
DM
Maximum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
NOP
BA a, COL b
t_DQSS (max)
DI a-b
NOP
NOP
t_WR
PRE
BA (a or all)
t_RP
Minimum DQSS
T1
T2
T3
T4
T5
T6
Write
NOP
NOP
BA a, COL b
t_DQSS (min)
DI a-b
NOP
NOP
t_WR
PRE
BA (a or all)
t_RP
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
t_WR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
Don’t Care
Figure 26 Write to Precharge: Non-Interrupting (Burst Length = 4)
Data Sheet
50
Rev. 1.2, 2004-06