HYB25D512800BT Datasheet, PDF (35/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
CK
CK
Command
Address
DQS
DQ
CAS Latency = 2
Read
BAa, COL n
NOP
CL=2
NOP
Read
BAa, COL b
NOP
DO a-n
NOP
DOa- b
CK
CK
Command
Address
Read
BAa, COL n
DQS
DQ
NOP
NOP
CL=2.5
Read
BAa, COL b
DO a-n
CAS Latency = 2.5
NOP
NOP
NOP
DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).
Shown with nominal t_AC, t_DQSCK, and t_DQSQ.
Don’t Care
Figure 12 Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
Data Sheet
35
Rev. 1.2, 2004-06