HYB25D512800BT Datasheet, PDF (28/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
Auto Pre charge
Auto Pre charge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction
with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write
command is automatically performed upon completion of the Read or Write burst. Auto Pre charge is non
persistent in that it is either enabled or disabled for each individual Read or Write command. Auto Pre charge
ensures that the pre charge is initiated at the earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge (t_RP) is completed. This is determined as if an explicit Pre charge
command was issued at the earliest possible time, as described for each burst type in Chapter 3.5.
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Pre charge disabled). The most recently
registered Read command prior to the Burst Terminate command is truncated, as shown in Chapter 3.5.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR)
Refresh in previous DRAM types. This command is non persistent, so it must be issued each time a refresh is
required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care”
during an Auto Refresh command. The 512Mbit Double Data Rate SDRAM requires Auto Refresh cycles at an
average periodic interval of 7.8 µs (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the
maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is
9 × 7.8 µs (70.2 µs). This maximum absolute interval is short enough to allow for DLL updates internal to the DDR
SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in t_AC between updates.
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self
Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is
automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh
(200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are
“Don’t Care” during Self Refresh operation. Since CKE is an SSTL_2 input , V_REF must be maintained during SELF
REFRESH.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE
returning high. Once CKE is high, the SDRAM must have NOP commands issued for t_XSNR because time is
required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and
DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
Data Sheet
28
Rev. 1.2, 2004-06