HYB25D512800BT Datasheet, PDF (52/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (Burst Length = 4 or 8)
CK
CK
Command
Address
DQS
DQ
DM
T1
T2
T3
T4
T5
Write
NOP
NOP
BA a, COL b
t_DQSS (min)
NOP
t_WR
2
PRE
BA (a or all)
DI a-b
3
4
4
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 1 data element is written.
t_WR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.
Figure 28 Write to Precharge: Minimum DQSS, Odd Number of Data, Interrupting
T6
NOP
t_RP
Don’t Care
Data Sheet
52
Rev. 1.2, 2004-06