HYB25D512800BT Datasheet, PDF (12/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Pin Configuration
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 3 (60 pins). The abbreviations used in the
Pin#/Buffer# column are explained in Table 4 and Table 5 respectively. The pin numbering for FBGA is depicted
in Figure 1 and that of the TSOP package in Figure 2
Table 3 Pin Configuration of DDR SDRAM
Ball#/Pin#
Name Pin Buffer Function
Type Type
Clock Signals
G2, 45
CK
I
SSTL Clock Signal
G3, 46
CK
I
SSTL Complementary Clock Signal
H3, 44
CKE
I
SSTL Clock Enable Rank
Control Signals
H7, 23
RAS
I
SSTL Row Address Strobe
G8, 22
CAS
I
SSTL Column Address Strobe
G7, 21
WE
I
SSTL Write Enable
H8, 24
CS
I
SSTL Chip Select
Address Signals
J8, 26
BA0
I
SSTL Bank Address Bus 2:0
J7, 27
BA1
I
SSTL
K7, 29
A0
I
SSTL Address Bus 11:0
L8, 30
A1
I
SSTL
L7, 31
A2
I
SSTL
M8, 32
A3
I
SSTL
M2, 35
A4
I
SSTL
L3, 36
A5
I
SSTL
L2, 37
A6
I
SSTL
K3, 38
A7
I
SSTL
K2, 39
A8
I
SSTL
J3, 40
A9
I
SSTL
K8, 28
A10
I
SSTL
AP
I
SSTL
J2, 41
A11
I
SSTL
H2, 42
A12
I
SSTL Address Signal 12
Note: 256 Mbit or larger dies
NC
NC
—
Note: 128 Mbit or smaller dies
F9, 17
A13
I
SSTL Address Signal 13
Note: 1 Gbit based dies
NC
NC
—
Note: 512 Mbit or smaller dies
Data Sheet
12
Rev. 1.2, 2004-06