HYB25D512800BT Datasheet, PDF (59/90 Pages) Infineon Technologies AG – 512Mbit Double Data Rate SDRAM

HYB25D512[40/16/80]0B[E/F/C/T]
512Mbit Double Data Rate SDRAM
Functional Description
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads
or Writes with Auto Precharge disabled.
8) Requires appropriate DM masking.
9) Concurrent Auto Precharge:
This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is
enabled any command may follow to the other banks as long as that command does not interrupt the read or write data
transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The
minimum delay from a read or write command with auto precharge enable, to a command to a different banks is
summarized in Table 13.
10) A Write command may be applied after the completion of data output.
Table 13 Truth Table 5: Concurrent Auto Precharge
From Command
To Command (different bank)
WRITE w/AP
Read w/AP
Read or Read w/AP
Write to Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
1) RU means rounded to the next integer
Minimum Delay with Concurrent
Auto Precharge Support
1 + (BL/2) + RU(t_WTR/t_CK)¹⁾
BL/2
1
BL/2
RU(CL)¹⁾ + BL/2
1
Unit
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
3.5.6 Input Clock Frequency Change
DDR SDRAM Input clock frequency cannot be changed during normal operation. Clock frequency change is only
permitted during Self Refresh or during Power Down. In the latter case the following conditions must be met:
DDR SDRAM must be in pre charged mode with CKE at logic Low level. After a minimum of 2 clocks after CKE
goes LOW, the clock frequency may change to any frequency between minimum and maximum operating
frequeny specified for the particular speed grade. During an input clock frequency change, CKE must be held
LOW. Once the input clock frequency is changed, a stable clock must be provided to DRAM before pre charge
power down mode may be exited. The DLL must be RESET via EMRS after pre charge power down exit. An
additional MRS command may need to be issued to appropriately set CL etc.. After the DLL relock time, the DRAM
is ready to operate with the new clock frequency.
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Data Sheet
59
Rev. 1.2, 2004-06