82P33714_17 Datasheet, PDF (9/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
2
PIN DESCRIPTION
Table 1: Pin Description
Pin No.
6
58
59
52
7
8
9
31
32
33
34
35
36
38
39
37
41
43
44
Name
OSCI
MS/SL
SONET/SDH/
LOS3
RSTB
XO_FREQ0/
LOS0
XO_FREQ1/
LOS1
XO_FREQ2/
LOS2
IN1_POS
IN1_NEG
IN2_POS
IN2_NEG
IN3_POS
IN3_NEG
IN4_POS
IN4_NEG
IN5
IN6
FRSYNC
_8K_1PPS
MFRSYNC
_2K_1PPS
I/O
Type
Description
Global Control Signal
OSCI: Crystal Oscillator System Clock
I
CMOS A clock provided by a crystal oscillator is input on this pin. It is the system clock for the
device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2
I
pull-up
I
pull-down
I
pull-up
CMOS
CMOS
CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit, controls whether the device is configured as the
Master or as the Slave. The signal level on this pin is reflected by the MASTER_SLAVE bit.
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit:
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
LOS3- This pin is used to disqualify input clocks. See input clocks section for more details.
RSTB: Reset
Refer to section 2.2 reset operation for details.
I
pull-down
CMOS
XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency.
XO_FREQ[2:0] Oscillator Frequency (MHz)
000
10.000
001
12.800
010
13.000
011
19.440
100
20.000
101
24.576
110
25.000
111
30.720
LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for
more details. After reset, this pin takes on the operation of LOS0-LOS2
Input Clock and Frame Synchronization Input Signal
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
I
PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN2_POS / IN2_NEG: Positive / Negative Input Clock 1
I
PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN3_POS / IN3_NEG: Positive / Negative Input Clock 3
I
PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN4_POS / IN4_NEG: Positive / Negative Input Clock 4
I
PECL/LVDS A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
I
pull-down
CMOS
IN5: Input Clock 5
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
I
pull-down
CMOS
IN6: Input Clock 6
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
Output Frame Synchronization Signal
O
CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS sync signal is output on this pin.
O
CMOS
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
A 2 kHz signal or a 1PPS sync signal is output on this pin.
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017