82P33714_17 Datasheet, PDF (20/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
3.2.2.1.4 Pre-Locked2 Mode
In Pre-Locked2 mode, the DPLL1 output attempts to track the
selected input clock.
The Pre-Locked2 mode is a secondary, temporary mode.
3.2.2.1.5 Lost-Phase Mode
In Lost-Phase mode, the DPLL1 output attempts to track the selected
input clock.
The Lost-Phase mode is a secondary, temporary mode.
3.2.2.1.6 DCO control modes
Figure 7 show a high level diagram of the DCO control architecture, it
shows the DCO in DPLL1 being controlled. The DCO is a phase accu-
mulator running at an internal clock. The DCO is controlled by a digital
word that can represent phase offset or frequency offset. In the case of
an IEEE 1588 application, the external processor will run the clock
recovery servo algorithm and it will generate a frequency offset word to
control the DCO.
The DCO control modes can be set by registers DPLL1_operating_-
mode_cnfg for DPLL1.
Figure 7 shows the DCO being controlled by writing a frequency off-
set word into the DCO, then by changing temporarily the DCO’s fre-
quency, the phase of the clock (or 1PPS) being generated by the DCO
will also change. The output phase change is the product of the fre-
quency change times the duration for which the frequency change is
applied for. Because the DCO's frequency word has a very fine resolu-
tion, the output phase can be adjusted in very fine steps. In this case the
clock recovery servo algorithm controls the bandwidth and phase slope
limiting. The frequency offset word can be written into DPLL1_hold-
over_freq_cnfg[39:0] bits of frequency configuration registers for
DPLL12. This value is 2’s complement signed number. Total range is +/-
92 ppm, and the DCO programming resolution is [(77760 / 1638400) *
2^-48] or ~1.686305041e-10 ppm. The DCO resolution is affected by the
offset applied into the DCO, so when writing into the DCO, the program-
ming resolution is [(77760/1638400) * 2^-48] * (1 + offset-in-ppm / 1e6).
Controlling the DCO’s frequency for smaller fine resolution phase
changes is a good method, but for bigger phase changes it is better to
use the snap-alignment method. The snap phase alignment is fast but
only provides coarse adjustment. The 82P33714 allows for both the fine
phase adjustment by controlling the frequency of the DCO and the
coarse phase adjustment by snap-aligning the output clock (or 1PPS),
for details, see section 3.2.7.3 Output Phase control on page 33.
D PLL1
PD
LPF
+
F re q u e n cy
O ffse t
DCO
S yste m
C lo c k
O s c illa to r
O u tpu t
C lo ck
M icro p o rt
In te rface
M ic ro p o rt
Figure 7. DCO frequency offset control functional block diagram
3.2.2.1.7 Holdover Mode
In Holdover mode, the DPLL1 resorts to the stored frequency data
acquired in Locked mode to control its output. The DPLL1 output is not
phase locked to any input clock. The frequency offset acquiring method
is selected by the man_holdover bit, auto_avg bit, the hist_mode [1:0]
bits, and the avg_mode[1:0] bits in DPLL1_holdover_mode_cnfg regis-
ters as shown in Table 5.
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017