82P33714_17 Datasheet, PDF (36/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
5
MICROPROCESSOR INTERFACE
The microprocessor interface provides access to read and write the
registers in the device. The microprocessor interface supports I2C.
5.1 I2C SLAVE MODE
5.1.1
I2C DEVICE ADDRESS
The default value for the higher 4-bit address is 4’b1010, the 3-bit
address is set by pins I2C_AD2, I2C_AD1, and I2C_AD0.
5.1.2
I2C BUS TIMING
Figure 17 shows the definition of I2C bus timing.
SDA
tf
SCL
S
tSU: DAT
tf
tLOW
tr
tHD: STA
tHD: STA
tHD: DAT
tHIGH
tSU: STA
Sr
Figure 17. Definition of I2C Bus Timing
tSP
tr
tBUF
tSU: STO
P
S
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017