82P33714_17 Datasheet, PDF (51/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
8.3.3.2 LVDS Output Port
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termi-
nation impedance (ZT) is between 90 and 132. The actual value
should be selected to match the differential impedance (Z0) of your
transmission line. A typical point-to-point LVDS design uses a 100 par-
allel resistor at the receiver and a 100 differential transmission-line
environment. In order to avoid any transmission-line reflection issues,
the components should be surface mounted and must be placed as
close to the receiver as possible. IDT offers a full line of LVDS compliant
devices with two types of output structures: current source and voltage
source. The standard termination schematic as shown at the top part of
Figure 31 can be used with either type of output structure. The termina-
tion schematic shown at the bottom part of Figure 31, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output structure is cur-
rent source or voltage source type. In addition, since these outputs are
LVDS compatible, the input receiver’s amplitude and common-mode
input range should be verified for compatibility with the output.
Figure 31. Recommended LVDS Output Port Line Termination
Table 28: LVDS Output Port Electrical Characteristics
Parameter
V_OD
V_OD
V_OS
V_OS
t_RISE/t_FALL
Description
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
Output Rise/Fall time
Min
Typ
Max
Unit
247
454
mV
50
mV
1.125
1.375
V
50
mV
90
400
ps
Test Condition
20% to 80%
©2017 Integrated Device Technology, Inc.
51
Revision 6, January 23, 2017