82P33714_17 Datasheet, PDF (12/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
Table 1: Pin Description (Continued)
Pin No.
40, 62
42, 53
19,23
73 (e_PAD)
56
Name
VDDD
VDDD_1_8
VSSAO
VSS
I/O
Power
Power
Ground
Ground
IC
-
Type
Description
VDDD: Digital Core Power - +3.3V DC nominal
VDDD_1_8: Digital Core Power - +1.8V DC nominal
VSSAO: Ground
-
VSS: Ground
Other
-
IC: Internal Connection
Internal Use. This pin must be left open for normal operation.
2.1 RECOMMENDATIONS FOR UNUSED INPUT
AND OUTPUT PINS
2.1.1
INPUTS
Control Pins
All control pins have internal pull-ups or pull-downs; additional resis-
tance is not required but can be added for additional protection. A 1kΩ
resistor can be used.
Single-Ended Clock Inputs
For protection, unused single-ended clock inputs should be tied to
ground.
Differential Clock Inputs
For applications not requiring the use of a differential input, both
*_POS and *_NEG can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from _POS to ground.
2.1.2
OUTPUTS
Status Pins
For applications not requiring the use of a status pin, we recommend
bringing out to a test point for debugging purposes.
Single-Ended Clock Outputs
All unused single-ended clock outputs can be left floating, or can be
brought out to a test point for debugging purposes.
Differential Clock Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
2.2 RESET OPERATION
The device must be reset properly in order to ensure operations
conform with specification.
To properly reset the device, the RSTB pin must be held at a low
value for at least 50 usec. The device should be brought out of reset
only at the time when power supplies are stabilized and the system
clock is available on OSCi pin. The RSTB can be held low until this time,
or pulsed low for at least 50us after this time.
The bootstrap pins (XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:0],
MS/SL, SONET/SDH) need to be held at desired states for at least 2ms
after de-assertion of RSTB pin to allow correct sampling. See Figure 3
for detail.
If loading from an EEPROM, the maximum time from RSTB de-
assert to have stable clocks is 100ms. Note that if there is a bad
EEPROM read sequence and the EEPROM loading is repeated once or
twice (three times halts the device), then this time can be 2 or 3 times
longer respectively. If not loading from EEPROM the maximum time
from RSTB de-assert to have stable clocks is 10ms.
An on-board reset circuit or a commercially available voltage
supervisory can be used to generate the reset signal. It is also feasible
to use a standalone power-up RC reset circuit. When using a power-up
RC reset circuit, careful consideration must be taken into account to fine
tune the circuit properly based on each power supply's specification to
ensure the power supply rise time is fast enough with respect to the RC
time constant of the RC circuit.
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017