82P33714_17 Datasheet, PDF (53/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
8.4 JITTER PERFORMANCE
Table 30: Gigabit Ethernet Output Clock Jitter Generation
(jitter measured on one differential output of APLL1/2 with one differential output enabled)
Output Frequency
RMS Jitter Typ (ps)
RMS Jitter Max (ps)
0.70
0.96
25 MHz
0.55
0.73
0.27
0.34
Test Filter
2.5 kHz - 5 MHz
12 kHz - 5 MHz
637 kHz - 5 MHz
0.71
125MHz
0.56
0.19
1.00
2.5 kHz to 10 MHz
0.75
12 kHz - 20 MHz
0.24
637 kHz - 10 MHz
0.55
0.52
156.25MHz
0.23
0.74
12 kHz - 20 MHz
1.18
20 kHz - 40 MHz
0.31
1 MHz - 30 MHz
0.17
0.24
1.875 MHz - 20 MHz
0.56
0.52
625MHz
0.16
0.76
12 kHz - 20 MHz
0.65
20 kHz - 80 MHz
0.29
1 MHz - 30 MHz
0.10
0.26
1.875 MHz - 20 MHz
NOTE 1: DPLL locked to input clock
NOTE 2: For BER = 10–12, RMS jitter = p-p jitter/13.8 per IEEE 802.3-2008 and IEEE 802.3ae-2002 section 48B.3.1.3.1
Notes
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 0.8 ns)
IEEE 802.3-2008
limit 0.24 UI p-p /
0.0174 UI RMS
(1 UI = 0.8 ns)
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 0.8 ns)
IEEE 802.3-2008
limit 0.24 UI p-p /
0.0174 UI RMS
(1 UI = 0.8 ns)
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 100.47 ps)
IEEE 802.3-2008
limit 0.28 UI p-p /
0.0203 UI RMS
(1 UI = 100.47 ps)
ITU-T G.8262 limit 0.5 UI p-p
0.0203 UI RMS
(1 UI = 100.47 ps)
IEEE 802.3-2008
limit 0.28 UI p-p /
0.0203 UI RMS
(1 UI = 100.47 ps)
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017