82P33714_17 Datasheet, PDF (13/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

VDDD
VDDA
OSCI
RSTB
Bootstrap
Pins*
50ȝs
2ms
* Bootstrap pins are: XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:0], MS/SL, SONET/SDH
Figure 3. Reset timing diagram
82P33714 Datasheet
©2017 Integrated Device Technology, Inc.
13
Revision 6, January 23, 2017