82P33714_17 Datasheet, PDF (32/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
DPLL selected input clock is within the limit. If it is within the limit,
whether frame/sync input signal is enabled to synchronize the frame
sync output signal is determined by the AUTO_EXT_SYNC_EN bit and
the EXT_SYNC_EN bit.
When the frame/sync input signal is enabled to synchronize the
frame/sync output signal, it is adjusted to align itself with the DPLL
selected input clock.
By default, the falling edge of the frame/sync input signal is aligned
with the rising edge of the DPLL1 selected input clock. The rising edge
of frame/sync input signal can be set to be aligned with the rising edge
of the DPLL1 selected input clock by setting sync_edge bit to “1” in
DPLL1_sync_edge_cnfg register.
The EX_SYNC_ALARM_MON bit indicates whether frame/sync
input signal is in external sync alarm status. The external sync alarm is
indicated by the EX_SYNC_ALARM bit. If the EX_SYNC_ALARM bit is
‘1’, the occurrence of the external sync alarm will trigger an interrupt.
The 8 kHz frame pulse, the 2 kHz frame pulse, and the 1PPS sync
signal can be inverted by setting the 8K_1PPS_INV and 2K_1PPS_INV
bits of Frame Sync and Multiframe Sync Output Configuration Register.
The 8 kHz and the 2 kHz frame sync outputs can be 50:50 duty cycle
or pulsed, as determined by the 8K_PUL and 2K_PUL bits respectively.
When they are pulsed, the pulse width derived from DPLL1 is defined by
the period of OUT1. They are pulsed on the position of the falling or ris-
ing edge of the standard 50:50 duty cycle, as selected by the
2K_8K_PUL_POSITION bit of Frame Sync and Multiframe Sync Output
Configuration Register.
3.2.7 INPUT AND OUTPUT PHASE CONTROL
The device has several features to allow a tight control of the phase
on the input and output clocks.
3.2.7.1 DPLL1 Phase offset control
The phase offset of the DPLL1 selected input clock with respect to
the DPLL1 output can be adjusted. If the device is configured as the
active PLL in a redundancy system, then the PH_OFFSET_EN bit deter-
mines whether the input-to-output phase offset is enabled. If the device
is configured as the inactive PLL in a redundancy system, then the
input-to-output phase offset is always enabled. If enabled, the input-to-
output phase offset can be adjusted by setting the PH_OFF-
SET_CNFG[28:0] bits in DPLL1 phase offset configuration register. The
register value is a 2's complement phase offset with a resolution of
0.0745ps and a total range of [20us, - 20us].
The input-to-output phase offset can be calculated as follows:
Phase Offset (ps) = PH_OFFSET[28:0] X 0.0745
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Revision 6, January 23, 2017