82P33714_17 Datasheet, PDF (31/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
Figure 15 shows the diagram for OUT2 to OUT7 output dividers and
relevant register bits.
APLL_PATH
DPLL1
DPLL2
APLL1
APLL2
Output Dividers
Output Div1
(OUTn_DIV1_CNFG[4:0]
2<n<4 (from APLL1)
5<n<7 (from APLL2)
Phase 1
Output Div2
(OUTn_DIV2_CNFG[26:0]
2<n<4 (from APLL1)
5<n<7 (from APLL2)
Phase 2
2<n<4 (from APLL1)
OUTn _{5<n<7 (from APLL2)}
Figure 15. OUT2 to OUT7 output dividers
OUT9 and OUT10 are derived from DPLL2, there is an output divider
associated with it. A GUI (Time Commander) can be used to set the fol-
lowing bis in the respective register that are associated with the DPLL2
dividers.
• To set the feedback divider, program DPLL2_fb_div_cnfg[13:0]
bits of DPLL2 feedback divider register
• To set the fractional divider, program DPLL2_divn_-
frac_cnfg[23:0] of DPLL2 fractional divider register
• To set the denominator of the fractional divider, program
DPLL2_divn_den_cnfg[15:0] bits of DPLL2 fractional divider
denominator register
• To set the numerator of the fractional divider, program
DPLL2_divn_num_cnfg[15:0] bits of DPLL2 fractional divider
numerator register
• To set the integer divider, program DPLL2_int_cnfg[7:0]bits of
DPLL2 integer divider register
OUT1 to OUT10 output clocks can be inverted by setting OUTn_IN-
VERT bit (0: output not inverted, 1: output inverted) in OUTn_MUX-
_CNFG register for (1 < n < 8), and in OUT9_CNFG and OUT10_CNFG
registers for OUT9 and OUT10 respectively.
The output clocks can be squelched by setting OUT-
n_SQUELCH[1:0] bits (0x: no squelch, 10: squelch to '0', 11: squelch to
'1') in OUTn_MUX_CNFG register for (1 < n < 8), and in OUT9_CNFG
and OUT10_CNFG registers for OUT1 to OUT8, and OUT9 and OUT10
respectively.
OUT1 to OUT8 output clocks can be individually powered down by
setting OUTn_PDN bit to '1' in OUTn_MUX_CNFG register for (1 < n <
8)
82P33714 provides a variety of output frequencies from 1Hz to
650MHz.
APLL1 is always enabled and the default frequency for OUT1, OUT2,
and OUT3 is respectively 25 MHz, 125 MHz, and 156.25MHz. OUT4 is
squelched by default.
By default, OUT5 to OUT8 are squelched. Set the proper registers to
set desired frequency values for OUT5 to OUT8.
DPLL2 is disabled by default, and if it is enabled, then the default fre-
quency for OUT9 and OUT10 is respectively 16.384 MHz and 2.048
MHz.
APLL1, APLL2, and the DPLLs can be configured from an external
EEPROM after reset. It can be used to set specific start up frequency
values as needed by the application.
3.2.6.2 Frame Sync Signals
Either an 8 kHz or a 2 kHz frame sync, or a 1PPS sync signal are
output on the FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS pins if
enabled by the 8K_1PPS_EN and 2K_1PPS EN bits respectively. They
are CMOS outputs.
The output sync frequencies are independent of the input sync fre-
quency. The output FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS fre-
quencies are selected through the DPLL1_fr_mfr_sync_cnfg registers.
Any supported clock frequency at the clock input can be associated
with the sync signals.
The frame sync output signals are derived from the DPLL1 and
DPLL2 output and are aligned with the output clock. They are synchro-
nized to the frame sync input signal. In DCO control modes (section
3.2.2.1.6), the output FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS
must not be used, a 1PPS output sync signal can be generated in any of
the output clocks connected to the DCO being used.
The frame sync output signals are derived from the DPLL1 output
and are aligned with the output clock. They are synchronized to the
frame sync input signal.
The frame/sync output signals align to the first edge of the associ-
ated reference clock that occurs after the edge of the frame/sync input
signal. The frequency of the associated reference clock must be lower or
equal to the frequencies of the output clocks that requires to be aligned
with the frame/sync pulse signal.
If the frame sync input signal with respect to the DPLL1 selected
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the frame/sync input signal is dis-
abled to synchronize the frame/sync output signals. The external sync
alarm is cleared once the frame/sync input signal with respect to the
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Revision 6, January 23, 2017