82P33714_17 Datasheet, PDF (24/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
The division factor is calculated as follows:
Division Factor = (the frequency of the clock input to the DivN
divider ÷ the frequency of the DPLL required clock set by the IN_-
FREQ[3:0] bits) - 1
The Pre-divider configuration and the division factor setting depend
on the input clock on one of the IN1 ~ IN6 pins and the DPLL required
clock.
For the fractional input divider, the FEC divider, each input clock has
a 16-bit (fec_divp_cnfg[15:0]) that represents the value of the numerator
and a 16-bit (fec_divq_cnfg[15:0]) that represents the value of the
denominator of FEC divider. The FEC division factor is calculated as fol-
lows:
FEC Division Factor = (fec_divp_cnfg[15:0]) ÷
(fec_divq_cnfg[15:0])
Pre-Divider
INn_DIV[1:0] bits
1<n<4
Input Clock INn
1<n<6
HF Divider
(for IN1 ~ IN4)
1
FEC Divider (P/Q)
0
DIRECT_DIV bit
LOCK_8K bit
00
DPLL
Clock
DivN Divider
1< n < 19440
01
Figure 9. Pre-divider for an input clock
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017