82P33714_17 Datasheet, PDF (3/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
HIGHLIGHTS ........................................................................................................................................................................... 5
FEATURES .............................................................................................................................................................................. 5
APPLICATIONS....................................................................................................................................................................... 5
DESCRIPTION......................................................................................................................................................................... 6
FUNCTIONAL BLOCK DIAGRAM .......................................................................................................................................... 7
1 PIN ASSIGNMENT ............................................................................................................................................................. 8
2 PIN DESCRIPTION ............................................................................................................................................................ 9
2.1 RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS ........................................................................................................... 12
2.1.1 Inputs .............................................................................................................................................................................................. 12
2.1.2 Outputs ........................................................................................................................................................................................... 12
2.2 RESET OPERATION...................................................................................................................................................................................... 12
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 14
3.1 SYNCHRONOUS ETHERNET, SONET AND SDH ARCHITECTURE ......................................................................................................... 14
3.2 HARDWARE FUNCTIONAL DESCRIPTION ................................................................................................................................................ 16
3.2.1 System clock .................................................................................................................................................................................. 16
3.2.2 Modes of operation ........................................................................................................................................................................ 16
3.2.2.1 DPLL1 Operating Mode .................................................................................................................................................... 16
3.2.2.2 DPLL2 Operating Mode ................................................................................................................................................... 22
3.2.3 Input Clocks and frame sync ........................................................................................................................................................ 23
3.2.3.1 Input Clock Pre-divider ..................................................................................................................................................... 23
3.2.3.2 Input Clock Quality Monitoring ......................................................................................................................................... 25
3.2.3.3 Input Clock Selection ........................................................................................................................................................ 27
3.2.4 DPLL Locking Process .................................................................................................................................................................. 28
3.2.4.1 Fast Loss .......................................................................................................................................................................... 28
3.2.4.2 Fine Phase Loss ............................................................................................................................................................... 29
3.2.4.3 Hard Limit Exceeding ....................................................................................................................................................... 29
3.2.4.4 Locking Status .................................................................................................................................................................. 29
3.2.4.5 Phase Lock Alarm ............................................................................................................................................................ 29
3.2.5 APLL1 and APLL2 .......................................................................................................................................................................... 29
3.2.5.1 EXTERNAL FILTER ......................................................................................................................................................... 30
3.2.6 Output Clocks & Frame Sync Signals .......................................................................................................................................... 30
3.2.6.1 Output Clocks ................................................................................................................................................................... 30
3.2.6.2 Frame Sync Signals ......................................................................................................................................................... 31
3.2.7 Input and output Phase control .................................................................................................................................................... 32
3.2.7.1 DPLL1 Phase offset control .............................................................................................................................................. 32
3.2.7.2 Input Phase control .......................................................................................................................................................... 33
3.2.7.3 Output Phase control ........................................................................................................................................................ 33
4 POWER SUPPLY FILTERING TECHNIQUES ................................................................................................................. 34
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 36
5.1 I2C SLAVE MODE ......................................................................................................................................................................................... 36
5.1.1 I2C Device Address ........................................................................................................................................................................ 36
5.1.2 I2C Bus Timing ............................................................................................................................................................................... 36
5.1.3 Supported Transactions ................................................................................................................................................................ 38
5.2 I2C MASTER MODE ..................................................................................................................................................................................... 38
5.2.1 I2C Boot-up Initialization Mode ..................................................................................................................................................... 39
5.2.2 EEPROM memory map notes ........................................................................................................................................................ 39
5.3 SERIAL MODE .............................................................................................................................................................................................. 40
5.4 UART MODE ................................................................................................................................................................................................. 42
5.4.1 Protocol ........................................................................................................................................................................................... 42
6 JTAG ................................................................................................................................................................................ 43
7 THERMAL MANAGEMENT ............................................................................................................................................. 44
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017