82P33714_17 Datasheet, PDF (47/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
8.3.2
8.3.2.1
LVPECL / LVDS INPUT / OUTPUT PORT
PECL Input Port
VDD (+ 3.3 V)
130 Ω
50 Ω (transmission line)
IN_POS
82 Ω
1 PPS
to
650 MHz
GND
VDD (+ 3.3 V)
130 Ω
50 Ω (transmission line)
82 Ω
IN_NEG
GND
Figure 24. Recommended PECL Input Port Line Termination
Table 25: LVPECL Input Port Electrical Characteristics
Parameter
Description
V_IL
Input Low Voltage, Differential Inputs
V_IH
Input High Voltage, Differential Inputs
V_ID
Input Differential Voltage
V_{IL_S}
Input Low Voltage, Single-ended Input
V_{IH_S}
Input High Voltage, Single-ended Input
I_IH
Input High Current, Input Differential Voltage V_ID = 1.4 V
I_IL
Input Low Current, Input Differential Voltage V_ID = 1.4 V
Note:
1. Assuming a differential input voltage of at least 100 mV.
2. Unused differential input terminated to VDD-1.4 V.
Min
VDD - 2.5
VDD - 2.4
0.1
VSS
VDD - 1.3
-10
Typ
VDD - 1.5
VDD - 1.4
0.7
VDD - 1.95
VDD - 0.9
Max
VDD - 0.5
VDD - 0.4
1.4
VDD - 1.5
VDD
10
Unit
Test Condition
V
V
V
V
V
A
A
©2017 Integrated Device Technology, Inc.
47
Revision 6, January 23, 2017