82P33714_17 Datasheet, PDF (59/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

Table 34: DPLL1/DPLL2 Output Clock Jitter Generation
(Jitter measured on one CMOS output of DPLL1/DPLL2 with all other outputs disabled)
Output Frequency
RMS Jitter Typ (ps)
RMS Jitter Max (ps)
10 MHz
N x 1.544 MHz
(Note 2)
100.11
100.63
16.06
619.64
543.45
39.94
N x 2.048 MHz
(Note 3)
99.42
10.66
449.83
26.44
34.368 MHz
101.67
25.62
202.75
39.06
44.736 MHz
105.16
20.77
NOTE 1:DPLL1/2 locked to input clock
NOTE 2: Measured on 12.352 MHz output clock
NOTE 3: Measured on 16.384 MHz output clock
198.15
27.44
Table 35: DPLL3 Output Clock Jitter Generation
(Jitter measured on one CMOS output of DPLL3 with all other outputs disabled)
Output Frequency
N x 2.048 MHz
Note 2
RMS Jitter Typ (ps)
147.325
8.02
RMS Jitter Max (ps)
347.530
17.24
N x 1.544 MHz
Note 3
133.88
0.80
303.43
1.47
NOTE 1:DPLL3 locked to input clock
NOTE 2: Measured on 12.288 MHz output clock
NOTE 3: Measured on 12.352 MHz output clock
Test Filter
100 Hz - 100 kHz
100 Hz - 40 kHz
8 kHz - 40 kHz
100 Hz - 100 kHz
18 kHz - 100 kHz
100 Hz - 800 kHz
10 kHz - 800 kHz
100 Hz - 400 kHz
30 kHz - 400 kHz
Test Filter
100 Hz - 100 kHz
18 kHz - 100 kHz
100 Hz - 40 kHz
8 kHz - 40 kHz
82P33714 Datasheet
Notes
ANSI T1.403
limit 0.07 UI p-p
(DS1: 1 UI = 647 ns)
ITU-T G.823
limit 0.2 UI p-p
(E1: 1 UI = 488 ns)
ITU-T G.751
limit 0.05 UI p-p
(E3: 1 UI = 29.10 ns)
Notes
ITU-T G.823
limit 0.2 UI p-p
(E1: 1 UI = 488 ns)
ANSI T1.403
limit 0.07 UI p-p
(DS1: 1 UI = 647 ns)
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017