82P33714_17 Datasheet, PDF (16/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
3.2 HARDWARE FUNCTIONAL DESCRIPTION
3.2.1 SYSTEM CLOCK
A crystal oscillator should be used as an input on the OSCI pin. This
clock is provided for the device as a system clock. The system clock is
used as a reference clock for all the internal circuits. The active edge of
the system clock can be selected by the OSC_EDGE bit in xo_freq_cnfg
register.
Eight common oscillator frequencies can be used for the stable Sys-
tem Clock. The oscillator frequency can be set by pins or by xo_fre-
q_cnfg register as shown in Table 2.
Table 2: Oscillator Frequencies
xo_freq[2:0] pins
xo_freq_cnfg[2:0] bits
Oscillator Frequency (MHz)
000
10.000
001
12.800
010
13.000
011
19.440
100
20.000
101
24.576
110
25.000
111
30.720
An offset from the nominal frequency may be compensated by set-
ting the NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is
within ±741 ppm.
The crystal oscillator should be chosen accordingly to meet different
applications and standard requirements. (See AN-807 Recommended
Crystal Oscillators for NetSynchro WAN PLL).
3.2.2 MODES OF OPERATION
3.2.2.1 DPLL1 Operating Mode
The DPLL1 can operate in several different modes as shown in
Table 3.
The DPLL1 operating mode is controlled by the DPLL1_OPERAT-
ING_MODE[4:0] bits.
Table 3: DPLL1 Operating Mode Control
DPLL1_OPERATING_MODE[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000-01001
01010
10010 - 11111
10011-11111
DPLL1 Operating Mode
Automatic
Forced - Free-Run
Forced - Holdover
Reserved
Forced - Locked
Forced - Pre-Locked2
Forced - Pre-Locked
Forced - Lost-Phase
Reserved
DCO write frequency
see Chapter 3.2.2.1.6
Reserved
Reserved
When the operating mode is switched automatically, the operation of
the internal state machine is shown in Figure 6.
Whether the operating mode is under external control or is switched
automatically, the current operating mode is always indicated by the
DPLL1_OPERATING_STS[4:0] bits. When the operating mode
switches, the DPLL1_OPERATING_STS bit will be set. If the
DPLL1_OPERATING_STS bit is ‘1’, an interrupt will be generated if the
corresponding mask bit is set to “1”, the mask bit is set to “0” by default.
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017