82P33714_17 Datasheet, PDF (17/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

1
Free-Run m ode
3
2
4
Pre-Locked
mode
5
Locked
10
mode
9
8
7
6
Holdover
mode
15
Pre-Locked2
mode
11
12
Lost-Phase
mode
13
14
Figure 6. DPLL Automatic Operating Mode
Notes to Figure 6:
1. Reset.
2. An input clock is selected.
3. The DPLL selected input clock is disqualified AND No qualified input clock is available.
4. The DPLL selected input clock is switched to another one.
5. The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’).
6. The DPLL selected input clock is disqualified AND No qualified input clock is available.
7. The DPLL selected input clock is unlocked (the DPLL_LOCK bit is ‘0’).
8. The DPLL selected input clock is locked again (the DPLL_LOCK bit is ‘1’).
9. The DPLL selected input clock is switched to another one.
10. The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’).
11. The DPLL selected input clock is disqualified AND No qualified input clock is available.
12. The DPLL selected input clock is switched to another one.
13. The DPLL selected input clock is disqualified AND No qualified input clock is available.
14. An input clock is selected.
15. The DPLL selected input clock is switched to another one.
The causes of Item 4, 9, 12, 15 - ‘the DPLL selected input clock is
switched to another one’ - are: (The DPLL selected input clock is dis-
qualified AND Another input clock is switched to) OR (In Revertive
switching, a qualified input clock with a higher priority is switched to) OR
(The DPLL selected input clock is switched to another one Forced selec-
tion).
82P33714 Datasheet
©2017 Integrated Device Technology, Inc.
17
Revision 6, January 23, 2017