82P33714_17 Datasheet, PDF (29/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
3.2.4.2 Fine Phase Loss
The DPLL compares the selected input clock with the feedback sig-
nal. If the phase-compared result exceeds the fine phase limit pro-
grammed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is
triggered. It is cleared once the phase-compared result is within the fine
phase limit.
For the greatest jitter and wander tolerance, set the
PH_LOS_FINE_LIMT[2:0] to the largest value.
The occurrence of the fine phase loss will result in DPLL to unlock if
the FINE_PH_LOS_LIMT_EN bit is ‘1’.
3.2.4.3 Hard Limit Exceeding
Two limits are available for this monitoring. They are DPLL soft limit
and DPLL hard limit. When the frequency of the DPLL output with
respect to the system clock exceeds the DPLL soft / hard limit, a DPLL
soft / hard alarm will be raised; the alarm is cleared once the frequency
is within the corresponding limit. The occurrence of the DPLL soft alarm
does not affect the DPLL locking status. The DPLL soft alarm is indi-
cated by the corresponding DPLL_SOFT_FREQ_ALARM bit. The
occurrence of the DPLL hard alarm will result in the DPLL to unlock if the
FREQ_LIMT_PH_LOS bit is ‘1’.
The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits
and can be calculated as follows:
DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724
The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]
bits and can be calculated as follows:
DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014
3.2.4.4 Locking Status
The DPLL locking status depends on the locking monitoring results.
The DPLL is in locked state if none of the following events is triggered
during 2 seconds; otherwise, the DPLL is unlocked.
• Fast Loss (the FAST_LOS_SW bit is ‘1’);
• Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
• DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).
If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the
FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the
DPLL locking status will not be affected even if the corresponding event
is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2
seconds.
The DPLL locking status is indicated by the corresponding
DPLL_LOCK bits and by the DPLL_LOCK pins.
3.2.4.5 Phase Lock Alarm
DPLL1 has a phase lock alarm that will be raised when the selected
input clock can not be locked in DPLL1 within a certain period. This
period can be calculated as follows:
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
The phase lock alarm is indicated by the corresponding
INn_PH_LOCK_ALARM bit (6  n  1).
The phase lock alarm can be cleared, as selected by the
PH_ALARM_TIMEOUT bit:
• It is cleared when a ‘1’ is written to the corresponding
INn_PH_LOCK_ALARM bit;
• It is cleared after the period (= TIME_OUT_VALUE[5:0] X MUL-
TI_FACTOR[1:0] in second) starting from the time the alarm is
raised.
The selected input clock with a phase lock alarm is disqualified for
the DPLL1 to lock.
Note that phase lock alarm is not available for DPLL2.
3.2.5 APLL1 AND APLL2
APLL1 and APLL2 are provided for a better jitter and wander perfor-
mance of the device output clocks. The bandwidth for APLL1 and APLL2
is internally set to 22 kHz (typical).
The input of both APLLs can be derived from one of the DPLL1 out-
puts, as selected by the apll1_path_freq_cnfg[2:0] and apll2_path_fre-
q_cnfg[2:0] bits respectively as shown in Table 10. APLL2 is free-
running by default, after reset APLL2 should be set to be connected to
DPLL1 per Table 10.
Table 10: APLL1/2 input selection
apll1/apll2_path_freq_cnfg[2:0]
000
001
010
011~1111
APLL1/2 Input Selection
622.08 MHz from DPLL1
625 MHz from DPLL1
644.53125 MHz from DPLL1
Reserved
To following steps should be followed to set APLL1/APLL2 output to
Ethernet LAN PHY frequencies.
To initialize the device, write into the following registers:
1. Write 0x04F4F0 to bits apll1/apll2_divn_frac_cnfg[20:0] of
APLL1/APLL2 fractional feedback divider configuration register
to set the fractional part of feedback divider for APLL1/APLL2
2. Write 0x0051 to bits apll1/apll2_divn_den_cnfg[15:0] of APLL1/
APLL2 divisor denominator configuration register to set the
denominator part of feedback divider for APLL1/APLL2
3. Write 0x0010 to bits apll1/apll2_divisor_num_cnfg[15:0] of
APLL1/APLL2 divisor numerator configuration register to set the
numerator part of feedback divider for APLL1/APLL2
4. Write 0x21 to bits apll1/apll2_divisor_int_cnfg[5:0] of APLL1/
APLL2 divisor integer configuration register to set the integer part
of feedback divider for APLL1/APLL2
5. Write 0x13356218 to bits apll1/apll2_fr_ratio_cnfg[28:0] of
APLL1/APLL2 feedback divider configuration register to set the
feedback divider for APLL1/APLL2
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Revision 6, January 23, 2017