82P33714_17 Datasheet, PDF(33/64 Page) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

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82P33714_17 Datasheet, PDF (33/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

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82P33714 Datasheet

3.2.7.2 Input Phase control

All the inputs phase can be controlled individually. They can be pro-

grammed with a resolution of 0.61 ns and a range of [77.5 ns,-78.1ns] by

setting INn_PHASE_OFFSET_CNFG[7:0] bits (1 < n < 6) in the input

phase offset configuration register. The register value is a 2's comple-

ment phase offset, the default is zero. The programmed offset is auto-

matically applied to the DPLL1 when a particular input is selected. If the

manual DPLL1 phase offset control is used then the per-input phase off-

set is not applied.

3.2.7.3 Output Phase control

The output phase can be controlled individually for outputs OUT1 to

OUT8. There is the coarse phase control that allows the output phase to

be adjusted as low as 1.6ns. There is a fine phase adjustment that

allows the output phase to be adjusted as low as 187.27 ps. The total

range is +/-180o.

There are two registers associated with the coarse phase adjust-

ment, the OUTn_PH1_CNFG (1 < n < 8) and the OUTn_PH2_CNFG (1

< n < 8) registers. The OUTn_PH1_CNFG register is associated with

output divider 1 as shown in Figure 14 and Figure 15, the phase can be

adjusted by a step size that is equal to the period of the input of clock of

the output Div1, the number set in the OUTn_PH1_CNFG register

should not be larger than the number set in OUTn_DIV1_CNFG register.

The OUTn_PH2_CNFG register is associated with output divider 2 as

shown in Figure 14 and Figure 15, the phase can be adjusted by a step

size that is equal to the period of the input of clock of the output Div2, the

number set in the OUTn_PH2_CNFG register should not be larger than

the number set in OUTn_DIV2_CNFG register.

There is a register that is associated with the fine phase adjustment,

the OUTn_FINE_CNFG (1 < n < 8). For the fine phase adjustment, the

output clocks must be output from the APLLs, The phase can be

adjusted by a step size that is equal to the 1/2 of the period of the VCO.

For Ethernet clocks the VCO frequency is 2.5GHz, for Ethernet LAN

PHY the VCO frequency is 2.578125 GHz, and for SONET/SDH clocks

the VCO frequency is 2.48832 GHz. OUT1 can be output from the

DPLLs, and in that case the fine phase adjustment is not available, it is

only available if the clocks are output from the APLLs.

The output phase adjustments are not available for OUT9 and

OUT10.

Revision 6, January 23, 2017

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