82P33714_17 Datasheet, PDF (54/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

Table 31: Gigabit Ethernet Output Clock Jitter Generation
(Jitter measured on one CMOS output of APLL1/2 with one CMOS output enabled)
Output Frequency
RMS Jitter Typ (ps)
RMS Jitter Max (ps)
0.71
0.95
25 MHz
0.54
0.70
0.23
0.29
Test Filter
2.5 kHz - 5 MHz
12 kHz - 5 MHz
637 kHz - 5 MHz
0.78
125MHz
0.61
0.20
1.07
2.5 kHz to 10 MHz
0.78
12 kHz - 20 MHz
0.25
637 kHz - 10 MHz
NOTE 1: DPLL locked to input clock
NOTE 2: For BER = 10–12, RMS jitter = p-p jitter/13.8 per IEEE 802.3-2008 and IEEE 802.3ae-2002 section 48B.3.1.3.1
82P33714 Datasheet
Notes
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 0.8 ns)
IEEE 802.3-2008
limit 0.24 UI p-p /
0.0174 UI RMS
(1 UI = 0.8 ns)
ITU-T G.8262
limit 0.5 UI p-p
(1 UI = 0.8 ns)
IEEE 802.3-2008
limit 0.24 UI p-p /
0.0174 UI RMS
(1 UI = 0.8 ns)
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017