82P33714_17 Datasheet, PDF (30/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
After the device has been initialized according to the steps above,
follow the following steps when setting APLL1/APLL2 path to 644.53125
MHz:
• Write 1’b1 to dsm_cnfg_en bit to enable the preset programma-
ble feedback divider of APLL1/APLL2 configuration register
• Write the corresponding value in the apll1/apll2_path_fre-
q_cnfg[2:0] bits according to Table 10.
After the device has been initialized according to the steps 1 to 5
above, follow the following steps when setting APLL1/APLL2 path to
625MHz: or 622.08MHz
• Write 1’b0 to dsm_cnfg_en bit to disable the preset programma-
ble feedback divider of APLL1/APLL2 configuration register
• Write the corresponding value in the apll1/apll2_path_fre-
q_cnfg[2:0] bits according to Table 10.
3.2.5.1 EXTERNAL FILTER
It is recommended to use external filter component for better noise
suppression. The filter components are connected to VC1 for APLL1
and VC2 APLL2. Choosing the correct external components and having
a printed circuit board (PCB) layout is a key task for quality operation of
the APLLs external filter option. Figure 13 shows the APLL1 and APLL2
external filter components, and Table 11 shows the recommended val-
ues for Rs, Cs and Cp. The device has been characterized using these
parameters. The external loop filter components should be kept as close
as possible to the device. Loop filter traces should be kept short. Other
signal traces should be kept separated and not run underneath the
device, and loop filter components.
Table 11: APLL1 and APLL2 filter components
VC Filter Pin
External component
Rs ()
220
Cs (uF)
1
Cp (pF)
470
VC
Rs
Cs Cp
Figure 13. APLL External Filter
3.2.6 OUTPUT CLOCKS & FRAME SYNC SIGNALS
The device supports 10 output clocks and 2 frame sync output sig-
nals.
3.2.6.1 Output Clocks
OUT1 can be derived either from DPLL1 or APLL1 selected by out-
1_mux_cnfg[3:0].
OUT2 ~ OUT4 can be derived from APLL1.
OUT5 ~ OUT7 can be derived from APLL2.
OUT8 can be derived either from DPLL1 or APLL2 selected by out-
8_mux_cnfg[3:0].
OUT1 to OUT8 have an output divider associated with each output.
The divider is composed by 2 cascaded dividers, the first divider can be
programmed by writing into OUTn_DIV1_CNFG[4:0], the second divider
can be programmed by writing into OUTn_DIV2_CNFG[26:0].
Figure 14 shows the diagram for OUT1 and OUT8 output dividers
and relevant register bits.
APLL_PATH
OUT1_MUX_CNFG[3:0]
OUT8_MUX_CNFG[3:0]
DPLL1
DPLL2
APLL1/
APLL2
OOuuttppuuttDDiivviiddeerr
Output Div1
(OUT1_DIV1_CNFG[4:0]
(OUT8_DIV1_CNFG[4:0])
Output Div2
(OUT1_DIV2_CNFG[26:0]
(OUT8_DIV2_CNFG[26:0])
OUT1
OUT8
Figure 14. OUT1 and OUT8 output dividers
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017