82P33714_17 Datasheet, PDF (41/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

Table 14: Read Timing Characteristics in Serial Mode
Symbol
T
t_in
t_out
t_su1
t_su2
t_d1
t_d2
t_pw1
t_pw2
t_h1
t_h2
t_TI
Parameter
One cycle time of the master clock
Delay of input pad
Delay of output pad
Valid SDI to valid SCLK setup time
Valid CS to valid SCLK setup time
Valid SCLK to valid data delay time
CS rising edge to SDO high impedance delay time
SCLK pulse width low
SCLK pulse width high
Valid SDI after valid SCLK hold time
Valid CS after valid SCLK hold time (CLKE = 0/1)
Time between consecutive Read-Read or Read-Write accesses
(CS rising edge to CS falling edge)
Min
4
14
5T+10
5T+10
6
5
10
Typ
12.86
5
5
10
10
82P33714 Datasheet
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 21. Serial Write Timing Diagram
Table 15: Write Timing Characteristics in Serial Mode
Symbol
Parameter
Min
Typ
Max
Unit
T
One cycle time of the master clock
12.86
ns
t_in
Delay of input pad
5
ns
t_out
Delay of output pad
5
ns
t_su1
Valid SDI to valid SCLK setup time
4
ns
t_su2
Valid CS to valid SCLK setup time
14
ns
t_pw1
SCLK pulse width low
5T+10
ns
t_pw2
SCLK pulse width high
5T+10
ns
t_h1
Valid SDI after valid SCLK hold time
6
ns
t_h2
Valid CS after valid SCLK hold time
5
ns
t_TI
Time between consecutive Write-Write or Write-Read accesses
(CS rising edge to CS falling edge)
10
ns
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Revision 6, January 23, 2017