82P33714_17 Datasheet, PDF (27/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
3.2.3.3 Input Clock Selection
For DPLL1 and DPLL2, the DPLL1/2_INPUT_SEL[3:0] bits (register
DPLL1/2_input_sel_cnfg) determine the input clock selection, as shown
in Table 9:
Table 9: Input Clock Selection for DPLL1 and DPLL2
DPLL1/2 _INPUT_SEL[3:0]
0000
0001 ~ 0010
0011 ~ 0110
0111 ~ 1000
1001 ~ 1010
1011 ~ 1111
Input Clock Selection
Automatic selection
Reserved
Forced selection (IN1 ~ IN4)
Reserved
Forced selection (IN5 ~ IN6)
Reserved
3.2.3.3.1 Forced Selection
In Forced selection, the selected input clock is set by the DPLL1_IN-
PUT_SEL[3:0] and DPLL2_INPUT_SEL[4:0] bits. The results of input
clocks quality monitoring do not affect the input clock selection if Forced
selection is used.
3.2.3.3.2 Automatic Selection
In Automatic selection, the input clock selection is determined by
input clock being valid, priority and input clock configuration. The input
clock is declared valid depending on the results of input clock quality
monitoring (refer to Chapter 3.2.3.2). The input clock can be configured
to be valid and therefore be allowed to participate in the locking process
by setting to “0” the corresponding INn_VALID bit (6  n  1) in
DPLL_remote_input_valid_cnfg register, by default all the inputs are not
valid, and therefore the user must set the corresponding bit to “0” in
order to allow the DPLL to lock to a particular input clock. Within all the
qualified input clocks, the one with the highest priority is selected. The
priority is set by the corresponding INn_SEL_PRIORITY[3:0] bits in
DPLL_INn_sel_priority_cnfg (6 n  1). If more than one qualified input
clock INn is available, then it is important to set appropriate priorities to
the input clocks, two input clocks must not have the same priority. This
process is shown in Figure 12.
In pu t C lo ck V a lid a tio n
P rio rity
Inp u t co n fig u ra tio n
No
No
No
In pu t C lo ck Q u ality M o n ito rin g
(L O S , A ctivity, F re q u en cy)
IN n = '1 '
IN n_S E L_P R IO R ITY [3:0]
'0 0 0 0 '
IN n _ V A L ID = '0 '
Yes
Yes
Yes
A ll q u a lifie d in p u t clo cks a re a va ila b le fo r A u to m a tic se le ction
Figure 12. Qualified Input Clocks for Automatic Selection
3.2.3.3.2.1 Input Clock Validation
For all the input clocks, the input is declared valid depending on the
results of input clock quality monitoring (refer to Chapter 3.2.3.2). The
IN_NOISE_WINDOW bit should be set to ‘1’ if any of INn_FREQ[3:0] is
set for frequencies  8 kHz, by default it is set to ‘0’.
For DPLL1, the following conditions must be satisfied for the input
clock to be valid; otherwise, it is invalid.
• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is
‘0’);
• No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’;
• If the ULTR_FAST_SW bit is ‘1’, the DPLL selected input clock
misses less than (<) 2 consecutive clock cycles; if the ULTR_-
FAST_SW bit is ‘0’, this condition is ignored;
• LOS[3:0] are not set to disqualify the input clock
For DPLL2, the following conditions must be satisfied for the input
clock to be valid; otherwise, it is invalid.
• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);
• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is
‘0’);
• LOS[3:0] are not set to disqualify the input clock
The INn bit (6  n  1) indicates whether or not the clock is valid.
When the input clock changes from ‘valid’ to ‘invalid’, or from ‘invalid’ to
‘valid), the INn bit will be set. If the INn bit is ‘1’, an interrupt will be gen-
erated.
When the DPLL selected input clock has failed, i.e., the selected
input clock changes from ‘valid’ to ‘invalid’, the DPLL_MAIN_REF_-
FAILED bit will be set. If the DPLL_MAIN_REF_FAILED bit is ‘1’, an
interrupt will be generated.
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Revision 6, January 23, 2017