82P33714_17 Datasheet, PDF (23/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
3.2.2.2.3 Holdover Mode
In Holdover mode, the DPLL2 has 2 modes of operation for the hold-
over set by DPLL2_auto_avg bit in DPLL2_holdover_mode_cnfg regis-
ter.
DPLL2_auto_avg = 0: holdover frequency is the instantaneous value
of integral path just before entering holdover. If the DPLL2 was locked to
an input clock reference that has no in-band jitter/wander and was then
manually set to go into holdover, the initial frequency accuracy is
4.4X10-8 ppm.
DPLL2_auto_avg = 1: averaged frequency value is used as holdover
frequency. The holdover average bandwidth is about 1.5mHz. In this
mode the initial frequency offset is 1.1e-5ppm assuming that there is no
in-band jitter/wander at the input just before entering holdover state.
3.2.2.2.4 Frequency Offset Limit
The DPLL2 output is limited to be within the DPLL hard limit (refer to
Chapter 3.2.4.3).
3.2.3 INPUT CLOCKS AND FRAME SYNC
The 82P33714 has 6 input clocks that can also be used for frame
sync pulses.
The 82P33714 supports Telecom and Ethernet frequencies from
1PPS up to 650 MHz.
Any of the input clocks can be used as a frame pulse or sync signal.
The SYNC_sel[3:0] bits in INn_los_sync_cnfg (1 < n < 6) registers sets
which pin is used as frame pulse or sync signal.
IN1 to IN6 can be used for 2 kHz, 4 kHz or 8 kHz frame pulses or
1PPS sync signal.The input frequency should match the setting in the
sync_freq[1:0] bits in DPLL1_input_mode_cnfg register.
3.2.3.1 Input Clock Pre-divider
Each input clock is assigned an internal Pre-divider. The Pre-divider
can be used to divide the clock frequency down to a convenient fre-
quency, such as 8 kHz for the internal DPLL1. Note that T1 and E1 refer-
ences can exhibit substantial jitter with frequencies above 4 kHz. These
references should be applied to DPLL1 without being divided down to 8
kHz.
For IN1 ~ IN6, the DPLL required frequency is set by the correspond-
ing IN_FREQ[3:0] bits.
Table 8: IN_FREQ[3:0] DPLL Frequency
IN_FREQ[3:0] Bits
0000
0001
0010
0011
0100
0101
0110 - 1000
1001
1010
1011
1100
1101
1110
1111
DPLL Frequency
8 kHz
1.544 MHz/ 2.048 MHz (depends on SONET/ SDH bit)
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
Reserved
2 kHz
4 kHz
1 PPS
6.25 MHz
Reserved
25 MHz
Reserved
Each Pre-divider consists of an FEC divider and a DivN divider,.
IN1~IN4 also include an HF (High Frequency) divider. Figure 9 shows a
block diagram of the pre-dividers for an input clock.
For 1 PPS, 2 kHz, 4 kHz or 8 kHz input clock frequency only, the Pre-
divider should be bypassed by setting INn_DIV[1:0] bits = “0” (1 < n < 4),
DIRECT_DIV bit = “0”, and LOCK_8K bit = “0”. The corresponding IN_-
FREQ[3:0] bits should be set to match the input frequency.
The HF divider, which is available for IN1 ~ IN4, should be used
when the input clock is higher than () 162.5 MHz. The input clock can
be divided by 4, 5 or can bypass the HF divider, as determined by the
INn_DIV[1:0] bits (1 < n < 4).
The DivN divider can be bypassed, as determined by the
DIRECT_DIV bit and the LOCK_8K bit. When DivN divider is bypassed,
the corresponding IN_FREQ[3:0] bits should be set to match the input
frequency. DIVN must be bypassed on a reference clock input that is
also associated with another reference input used as SYNC.
When the DivN divider is used for INn (1  n  6), the division factor
setting should observe the following order:
1. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
2. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
©2017 Integrated Device Technology, Inc.
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Revision 6, January 23, 2017