82P33714_17 Datasheet, PDF (21/64 Pages) Integrated Device Technology – Synchronous Equipment Timing Source for Synchronous Ethernet

82P33714 Datasheet
Table 5: Frequency Offset Control in Holdover Mode
man_hold
over
auto_avg
0
hist_mode [1:0]
don’t-care
0
0
0
0
0
1
0
1
1
0
1
don’t-care
avg_mode[1:0]
don’t-care
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Frequency Offset Acquiring Method
Averaged
Current averaged value with holdover filter BW of ~0.18mHz
Current averaged value with holdover filter BW of ~1.5mHz
Current averaged value with holdover filter BW of ~12mHz
Current averaged value with holdover filter BW of ~0.15Hz
Averaged value 1 second before with holdover filter BW of ~0.18mHz
Averaged value 1 second before with holdover filter BW of ~1.5mHz
Averaged value 1 second before with holdover filter BW of ~12mHz
Averaged value 1 second before with holdover filter BW of ~0.15Hz
Averaged value 8 seconds before with holdover filter BW of ~0.18mHz
Averaged value 8 seconds before with holdover filter BW of ~1.5mHz
Averaged value 8 seconds before with holdover filter BW of ~12mHz
Averaged value 8 seconds before with holdover filter BW of ~0.15Hz
Averaged value 64 seconds before with holdover filter BW of ~0.18mHz
Averaged value 64 seconds before with holdover filter BW of ~1.5mHz
Averaged value 64 seconds before with holdover filter BW of ~12mHz
Averaged value 64 seconds before with holdover filter BW of ~0.15Hz
Manual - values is set by DPLL1_holdover_freq_cnfg register
The default value for holdover mode is set to current averaged value
with holdover filter BW of ~1.5mHz. In this mode the initial frequency off-
set is better than 1.1e-5ppm assuming that there is no in-band jitter/wan-
der at the input just before entering holdover state. The default mode is
used for Telcordia GR-1244, Telcordia GR-253, ITU-T G.8262 and ITU-T
G.813 to meet holdover requirements.
In Manual Mode, the frequency offset is set by the DPLL1_hold-
over_freq_cnfg[39:0] bits. The accuracy is1.686305041e-10 ppm, how-
ever the resolution is affected by the frequency offset applied, so when
writing the frequency offset, the programming resolution is [(77760/
1638400) * 2^-48] * (1 + offset-in-ppm / 1e6).
The offset value, which is acquired by the modes shown in Table 5,
can be read from the holdover_freq_cnfg[39:0] bits by setting the
read_avg bit to “1”. If read_avg bit is set to “0” then the value in hold-
over_freq_cnfg[39:0] bits is the value written into it. The value is 2’s
complement signed number, and the total range is +/- 92 ppm.
The holdover frequency resolution is calculated as follows:
Holdover Frequency resolution: HO_freq_res = (77760/1638400) *
2^-48
The Holdover value read from register bits holdover_freq_cnfg[[39:0]
must be converted to decimal:
HO_value_dec = holdover_freq_cnfg[39:0] value in decimal
The frequency offset in ppm is calculated as follows:
Holdover Frequency Offset (ppm) = (HO_freq_res * HO_value_dec)/
(1-((HO_freq_res * HO_value_dec)/1e6))
3.2.2.1.8 Hitless Reference Switching
Bit hitless_switch_en in DPLL1_mon_sw_pbo_cnfg register can be
used to set hitless reference switching. When a Hitless Switching (HS)
event is triggered, the phase offset of the selected input clock with
respect to the DPLL1 output is measured. The device then automatically
accounts for the measured phase offset and compensates for the appro-
priate phase offset into the DPLL output so that the phase transients on
the DPLL1 output are minimized. The input frequencies should be set to
frequencies equal to 8 kHz or higher.
If hitless_switch_en is set to “1”, a HS event is triggered if any one of
the following conditions occurs:
• DPLL1 selected input clock switches to a different reference
• DPLL1 exits from Holdover mode or Free-Run mode
For the two conditions, the phase transients on the DPLL1 output are
minimized to be no more than 0.61 ns with HS. The HS can also be fro-
zen at the current phase offset by setting the hitless_switch_freeze bit in
DPLL1_mon_sw_pbo_cnfg register. When the HS is frozen, the device
will ignore any further HS events triggered by the above two conditions,
and maintain the current phase offset.
When the HS is disabled, there may be a phase shift on the DPLL1
output, as the DPLL1 output tracks back to 0 degree phase offset with
respect to the DPLL1 selected input clock. This phase shift can be lim-
ited; see section 3.2.2.1.9 Phase Slope Limit.
©2017 Integrated Device Technology, Inc.
21
Revision 6, January 23, 2017