ICS1893Y-10 Datasheet, PDF (99/150 Pages) –

ICS1893Y-10 - Release
Chapter 7 Management Register Set
7.13.8 Link Loss Inhibit (bit 18.1)
The Link Loss Inhibit bit allows an STA to prevent the ICS1893Y-10 from dropping the link in 10Base-T
mode. When an STA sets this bit to logic:
• Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted-
Pair Receiver inputs.
• One, the ICS1893Y-10 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state
regardless of the Twisted-Pair Receiver input conditions.
7.13.9 Squelch Inhibit (bit 18.0)
The Squelch Inhibit bit allows an STA to control the ICS1893Y-10 Squelch Detection in 10Base-T mode.
When an STA sets this bit to logic:
• One, before the ICS1893Y-10 can establish a valid link, the ICS1893Y-10 must receive valid 10Base-T
data.
• Zero, before the ICS1893Y-10 can establish a valid link, the ICS1893Y-10 must receive both valid
10Base-T data followed by an IDL.
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
99
January, 2004