ICS1893Y-10 Datasheet, PDF (95/150 Pages) –

ICS1893Y-10 - Release
Chapter 7 Management Register Set
7.12.6 False Carrier (bit 17.8)
The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893Y-10 in 100Base
mode.
A False Carrier occurs when the ICS1893Y-10 begins evaluating potential data on the incoming 100Base
data stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic:
• Zero, it indicates a False Carrier has not been detected since either the last read or reset of this register.
• One, it indicates a False Carrier was detected since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
7.12.7 Invalid Symbol (bit 17.7)
The Invalid Symbol bit indicates to an STA the detection of an Invalid Symbol in a 100Base data stream by
the ICS1893Y-10.
When the ICS1893Y-10 is receiving a packet, it examines each received Symbol to ensure the data is error
free. If an error occurs, the port indicates this condition to the MAC/repeater by asserting the RXER signal.
In addition, the ICS1893Y-10 sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic:
• Zero, it indicates an Invalid Symbol has not been detected since either the last read or reset of this
register.
• One, it indicates an Invalid Symbol was detected since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
7.12.8 Halt Symbol (bit 17.6)
The Halt Symbol bit indicates to an STA the detection of a Halt Symbol in a 100Base data stream by the
ICS1893Y-10.
During reception of a valid packet, the ICS1893Y-10 examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. In addition, it looks for special symbols such as the Halt
Symbol. If a Halt Symbol is encountered, the ICS1893Y-10 indicates this condition to the MAC/repeater.
If this bit is set to a logic:
• Zero, it indicates a Halt Symbol has not been detected since either the last read or reset of this register.
• One, it indicates a Halt Symbol was detected in the packet since either the last read or reset of this
register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
7.12.9 Premature End (bit 17.5)
The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream
by the ICS1893Y-10.
During reception of a valid packet, the ICS1893Y-10 examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. If two consecutive Idles are encountered, it indicates
this condition to the MAC/repeater by setting this bit.
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
95
January, 2004