ICS1893Y-10 Datasheet, PDF (142/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.18 Reset: Hardware Reset and Power-Down
Table 9-25 lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REF_IN
• RESETn
• TXCLK
Figure 9-19 shows the timing diagram for the time periods.
Table 9-25. Hardware Reset and Power-Down Timing
Time
Period
Parameter
t1 RESETn Active to Device Isolation and Initialization
t2 Minimum RESETn Pulse Width
t3 RESETn Released to TXCLK Valid
Condi-
tions
–
–
–
Min. Typ. Max. Units
– 60 –
ns
500 40 –
ns
– 35 500 ms
Figure 9-19. Hardware Reset and Power-Down Timing Diagram
REF_IN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
142
January, 2004