ICS1893Y-10 Datasheet, PDF (125/150 Pages) –

ICS1893Y-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5 Timing Diagrams
9.5.1 Timing for Clock Reference In (REF_IN) Pin
Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. Figure 9-2
shows the timing diagram for the time periods.
Note: The REF_IN switching point is 50% of VDD.
Table 9-8. REF_IN Timing
Time
Period
Parameter
t1 REF_IN Duty Cycle
t2 REF_IN Period
Conditions
–
–
Min. Typ. Max. Units
40
50
60
%
–
40
–
ns
Figure 9-2. REF_IN Timing Diagram
t1
REF_IN
t2
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
125
January, 2004