ICS1893Y-10 Datasheet, PDF (127/150 Pages) –

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Chapter 9 DC and AC Operating Conditions
9.5.3 Timing for Receive Clock (RXCLK) Pins
Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various
interfaces. Figure 9-4 shows the timing diagram for the time periods.
Table 9-10. MII Receive Clock Timing
Time
Period
Parameter
t1 RXCLK Duty Cycle
t2a RXCLK Period
t2b RXCLK Period
t2c RXCLK Period
t2d RXCLK Period
Conditions
Min. Typ. Max. Units
–
35 50 65 %
100M MII (100Base-TX)
– 40 –
ns
10M MII (10Base-T)
– 400 –
ns
100M Symbol Interface (100Base-TX) – 40 –
ns
10M Serial Interface (10Base-T)
– 100 –
ns
Figure 9-4. Receive Clock Timing Diagram
t1
RXCLK
t2
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
127
January, 2004