ICS1893Y-10 Datasheet, PDF (7/150 Pages) –

ICS1893Y-10 - Release
Table of Contents
Table of Contents
Section
7.14
7.14.1
7.14.2
7.14.3
7.14.4
7.14.5
7.14.6
7.14.7
Chapter 8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Title
Page
Register 19: Extended Control Register 2 ...........................................................100
Node/Repeater Configuration (bit 19.15) .............................................................101
Hardware/Software Priority Status (bit 19.14) ......................................................101
Remote Fault (bit 19.13) ......................................................................................101
ICS Reserved (bits 19.12:8) .................................................................................101
Twisted Pair Tri-State Enable, TPTRI (bit 19.7) ...................................................102
ICS Reserved (bits 19.6:1) ...................................................................................102
Automatic 100Base-TX Power-Down (bit 19.0) ...................................................102
Pin Diagram, Listings, and Descriptions ..................................................................... 103
ICS1893Y-10 Pin Diagram ...................................................................................103
ICS1893Y-10 Pin Listings ....................................................................................104
ICS1893Y-10 Pin Descriptions ............................................................................105
Transformer Interface Pins ..................................................................................105
Multi-Function (Multiplexed) Pins: PHY Address and LED Pins ..........................106
Configuration Pins ................................................................................................109
MAC/Repeater Interface Pins ..............................................................................111
Reserved Pins ......................................................................................................120
Ground and Power Pins .......................................................................................120
Chapter 9
9.1
9.2
9.3
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
9.5.8
9.5.9
DC and AC Operating Conditions................................................................................. 121
Absolute Maximum Ratings .................................................................................121
Recommended Operating Conditions ..................................................................121
Recommended Component Values .....................................................................122
DC Operating Characteristics ..............................................................................123
DC Operating Characteristics for Supply Current ................................................123
DC Operating Characteristics for TTL Inputs and Outputs ..................................123
DC Operating Characteristics for REF_IN ...........................................................124
DC Operating Characteristics for Media Independent Interface ..........................124
Timing Diagrams ..................................................................................................125
Timing for Clock Reference In (REF_IN) Pin .......................................................125
Timing for Transmit Clock (TXCLK) Pins .............................................................126
Timing for Receive Clock (RXCLK) Pins ..............................................................127
100M MII / 100M Stream Interface: Synchronous Transmit Timing .....................128
10M MII: Synchronous Transmit Timing ..............................................................129
MII / 100M Stream Interface: Synchronous Receive Timing ................................130
MII Management Interface Timing .......................................................................131
10M Serial Interface: Receive Latency ................................................................132
10M Media Independent Interface: Receive Latency ...........................................133
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
7
January, 2004