ICS1893Y-10 Datasheet, PDF (141/150 Pages) –

ICS1893Y-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5.17 Reset: Power-On Reset
Table 9-24 lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
Figure 9-18 shows the timing diagram for the time periods.
Table 9-24. Power-On Reset Timing
Time
Period
Parameter
t1 VDD ≥ 2.7 V to Reset Complete
Conditions Min. Typ. Max. Units
–
40 45 500 ms
Figure 9-18. Power-On Reset Timing Diagram
VDD
2.7 V
t1
TXCLK
Valid
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
141
January, 2004