ICS1893Y-10 Datasheet, PDF (94/150 Pages) –

ICS1893Y-10 Data Sheet - Release
Chapter 7 Management Register Set
If Auto-Negotiation is enabled, these bits continually latch the highest state that the Auto-Negotiation State
Machine achieves. That is, they are updated only if the binary value of the next state is greater than the
binary value of the present state as outlined in Table 7-19.
Note: An MDIO read of these bits provides a history of the greatest progress achieved by the
auto-negotiation process. In addition, the MDIO read latches the present state of the
Auto-Negotiation State Machine for a subsequent read.
Table 7-19. Auto-Negotiation State Machine (Progress Monitor)
Auto-Negotiation State Machine
Idle
Parallel Detected
Parallel Detection Failure
Ability Matched
Acknowledge Match Failure
Acknowledge Matched
Consistency Match Failure
Consistency Matched
Auto-Negotiation Completed
Successfully
Auto-Negotiation Progress Monitor
Auto-
Negotiation
Complete Bit
(Bit 17.4)
Auto-
Negotiation
Monitor Bit 2
(Bit 17.13)
Auto-
Negotiation
Monitor Bit 1
(Bit 17.12)
Auto-
Negotiation
Monitor Bit 0
(Bit 17.11)
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
7.12.4 100Base-TX Receive Signal Lost (bit 17.10)
The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893Y-10 has lost its
100Base-TX Receive Signal. If this bit is set to a logic:
• Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register.
• One, it indicates the Receive Signal was lost since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
7.12.5 100Base PLL Lock Error (bit 17.9)
The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893Y-10 has ever
experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming
100Base data stream. If this bit is set to a logic:
• Zero, it indicates that a PLL Lock Error has not occurred since either the last read or reset of this register.
• One, it indicates that a PLL Lock Error has occurred since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)
Note: This bit has no definition in 10Base-T mode.
ICS1893Y-10 Rev F 1/20/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
94
January, 2004